No. 35 (211), issue 6Pages 41 - 53

RUSSIAN 3D-TORUS INTERCONNECT WITH GLOBALLY ADDRESSABLE MEMORY SUPPORT

A.A. Korzh, D.V. Makagon, A.A. Borodin, I.A. Zhabin, E.R. Kushtanov, E.L. Syromyatnikov, E.V. Cheryomushkina
This paper gives the overview and early results of prototyping of the 3d-torus interconnect developed in NICEVT, Moscow. This interconnect was designed to be equally effective in small-size computing clusters and petascale systems. The key features of the interconnect are high fault-tolerance, high message rate per core supported by host adapter and hardware support for globally addressable memory provided via SHMEM parallel programming library.
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Keywords
interconnection network, supercomputer, 3D-torus, globally addressable memory