Implementation of Surface-Related Multiple Prediction Problem on Reconfigurable Computer Systems

The traditional methodology of computer-aided synthesis of parallel-pipeline programs for reconfigurable computer systems based on field programmable gate arrays (FPGAs) is aimed at the highest possible computer system performance, achieved on available hardware resource. Application of such an approach to real-time problems can lead to inefficient use of system hardware resource. Frequently, this fact leads to idle stand of occupied equipment and to higher requirements to power consumption, size and cost of the end product. We suggest a new methodology to synthesize of parallel-pipeline programs for solution of real-time computationally intensive problems. The methodology provides data processing having a specified rate which depends on a specified time interval. With the help of the developed methodology, it is possible to synthesize a problem computing structure, which requires the minimum hardware resource for the specified system performance. In order to illustrate the suggested methodology, we give the solution of the real-time surface-related multiple prediction problem. We evaluate various configurations of reconfigurable computer systems based on Xilinx Kintex UltraScale FPGAs.

Keywords

reconfigurable computer systems; field programmable gate array (FPGA); surface-related multiple prediction (SRMP); real-time problems.

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